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Message-ID: | <53C55F5E.2070807@sonic.net> |
Date: | Tue, 15 Jul 2014 10:05:34 -0700 |
From: | Dave Curtis <davecurtis AT sonic DOT net> |
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To: | geda-user AT delorie DOT com |
Subject: | Re: [geda-user] thermal flag in footprint? |
References: | <53C5441E DOT 4090502 AT sonic DOT net> <201407151520 DOT s6FFKY9Q006882 AT envy DOT delorie DOT com> <53C5521F DOT 8090506 AT sonic DOT net> <201407151624 DOT s6FGOINF008965 AT envy DOT delorie DOT com> |
In-Reply-To: | <201407151624.s6FGOINF008965@envy.delorie.com> |
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Reply-To: | geda-user AT delorie DOT com |
On 07/15/2014 09:24 AM, DJ Delorie wrote: > "Holes" aren't plated through so they're useless for electrical > connectivity or heat sinks. ?? But if you put a hole through a board with polygon on both sides doesn't it plate? What keeps it from plating? > > You could also add a solder-side pad, so that the user only need > thermal the one pad instead of all the pins. This comes back to my clearance question. Assume a pad on the back. Clearance of zero is not wise according to your answer to an earlier question, and negative clearance is not a thing. So now with non-zero clearance, the pad clears the large polygon that the user draws over it. Pads don't thermal, you have to draw tracks over the gap. The snap-to-pad-centers behavior is not helpful while doing that. So given that with these parts you are often just going for a certain amount of area, however it fits, it seems like letting the user draw the back-side makes sense. There isn't a lot of value in including it in the footprint. >
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