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22 Dec 2015 13:14:10 -0800 (PST) | |
In-Reply-To: | <1512221837.AA25291@ivan.Harhan.ORG> |
References: | <1512221837 DOT AA25291 AT ivan DOT Harhan DOT ORG> |
Date: | Tue, 22 Dec 2015 21:14:10 +0000 |
Message-ID: | <CAJXU7q990v-KKB--=839DvsRHDg-QeaCb2bREziv0BoiNMH6rw@mail.gmail.com> |
Subject: | Re: [geda-user] Project leadership |
From: | "Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
To: | gEDA User Mailing List <geda-user AT delorie DOT com> |
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On 22 December 2015 at 18:37, Mychaela Falconia <falcon AT ivan DOT harhan DOT org> wrote: > My new non-graphical, text-based "schematic" design entry language is > the structural subset of Verilog (wires, ports and instantiations), > and I make very heavy use of hierarchy to make readable designs that > can be evaluated for correctness. Here is my current project done > with these tools: > > https://bitbucket.org/falconian/freecalypso-schem > > M~ I just spent a little time digging into your source files for that design... I am really impressed, and think the concept is excellent, especially how packages pins end up mapped neatly to signal names etc.. Structural VHDL or its analogue equivalent would probably have given you a few more language intrinsic ways to abstract things a little more - at the expense of driving people mad with all the extra typing. For me personally - I don't think it works as well for things like the analogue VCO. For that - I would prefer to see a gschem schematic, and a non-flattening net-list back-end which produces your verilog description as a secondary, generated output. (I'd understand that aspect of the circuit more readily then). Peter
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