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Date: Wed, 12 Jul 2017 20:55:15 +0200 (CEST)
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Subject: Re: [geda-user] PCB, load element bug (know then but not why)
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On Wed, 12 Jul 2017, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com] wrote:

> Sounds good.
>
> You have or are planning a tree like structure like this: root object layout --> sub circuits --> footprints --> pads --> drawing primitives?
>
> In sort of any object could appear anywhere? To connect with netlist it must be possible to find footprints by refdes and pin number but otherwise what is counted as a pad os circuit is more about where they are saved?

What I already have:

board -> primitives

board -> subcircuit -> primitives

What I plan to have:

board -> subcircuit -> subcircuit -> ... -> primitives

This also means a hierarchic pcb could reflect a hierarchic netlist which 
in turn could be derived from a hierarchic schematics (low prio, long 
term plan).

Pins & pads: I will implement what I've developed for tEDAx: there won't 
be a special pin or pad object any more, but there will be logical 
terminals. A terminal will have an ID, similar to pin or pad number now, 
and other, optional metadata (such as symbolic name). You would just tag 
any primitive within a subcircuit to belong to a specific terminal ID. 
Or in other words, your "pin 1" could constructed of a via, your "pad 2" 
could be a line, a polygon or even an arc, and your "pad 4" can be a 
combination of any of the above.

Since subcircuits are free of the layer restrictions as well, this 
also means you will be able to bind a mask cutout object to a specific 
terminal.

After this is done, I will remove the pin, pad, element, element-line, 
element-arc primitives from core.

Meanwhile I have a lower priority (due to lack of user demand) long term 
plan to turn via into padstack. I would also make the hole optional. The 
pad stack recipe would be able to install different polygon shapes on 
different layers, not restricted to copper layers, not required to have a 
pad on every layer. The optional hole would be part of this game. This 
would solve the pad stack and bbvia problems in an elegant, clean way and 
would produce the trivial pin/pad primitive for subcircuit. E.g. a pad is 
just a padstack without a hole, with a top copper polygon and a top mask 
cutout polygon. A pin can be built from a padstack that affects more 
copper layers, both mask layers and has a hole. Anything more complicated 
can be combined/built of individual lines, arcs, polygons, pad stacks and 
text objects by just tagging them all to the same terminal ID.

Regards,

Igor2