X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:content-type :content-transfer-encoding; bh=B1KHpSHDm2sv001OWY44b2iuVhoj6y2Q3bXtukq5r0o=; b=P8AFW8W4DvY7MyKBubAy7XCUVDN2fSjz5b8unqDi5aX+sbCWbdf2NhHtbxSn+tYoay f7lVagWHvxUsd+K1t8ilq/21424zjTHZJ/JmwbJ3M+pVHfDnx7cg+nFasYbC6EuMDOHx NwAbW7I4NMsHmddcpFfPcUbsfgMMTlam4XntPoGvGqVaNxiqcdBLLk3OFuFcZG83fjXs s6KiJi1iknX9cbcJb/5fSy6b7WWu5uAWs/v8k5Ih7t+5Vmz2xgpkZnq5tKfFKRkMb7wb enq3FPt8ykudJw5pHAq0wpjNE2vO8KHiMEilwFPWQamKBjDNyAv469ZtbHUghKYHD0Jm O+qA== MIME-Version: 1.0 Sender: silicon DOT on DOT inspiration AT gmail DOT com In-Reply-To: <4FCEC8F9.60509@studiofeed.com> References: <4FCE7A57 DOT 1010107 AT studiofeed DOT com> <4FCEC8F9 DOT 60509 AT studiofeed DOT com> Date: Wed, 6 Jun 2012 14:38:52 +1000 X-Google-Sender-Auth: d-Uk3TDr0sAm6zhWekStDiH_BxA Message-ID: Subject: Re: [geda-user] Clearance between polygons on same layer group From: Stephen Ecob To: geda-user AT delorie DOT com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by delorie.com id q5654Dfi012049 Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Wed, Jun 6, 2012 at 1:05 PM, Tim van Boxtel wrote: > Great reply! > > The information about the join flag was helpful and it works if there is > only one polygon on a physical layer.  Is there a way to force a clearance > between 2 polygons on different layers, yet the same layer group (i.e. > physical layer)? No, there is no way (currently) to force a clearance between 2 polygons in the same layer group. > I have found drawing the polygon with thick traces works as expected, though > it can be a touch cumbersome :) Yes, that's a commonly used workaround. Another workaround is to manually place your polygons, vertex by vertex, so that they have the desired clearance at each point. Tedious but do-able. Peter Clifton has a number of experimental branches of PCB that include cool features like anti-polygons and copper pours. Hopefully he'll find the time to merge these cool features into the PCB mainline at some stage, but even now they are available to experiment with: http://pcjc2.blogspot.com.au/2011/02/pcbgl-repository-instructions.html Of course these branches are not production code, so pay attention to Peter's caveats regarding their use.